The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabricated to insulate neighboring gate lines from each other.
With the increase in integration, limitations associated with the deposition of the insulating layer between gate lines become an important factor in determining the reliability of the semiconductor device. In the current fabrication method, as the gate line spacing gets smaller and the active regions get closer, a local step portion (or local step formation) is formed on the surface of an isolation structure insulating active regions from each other. A local step formation is formed when the isolation structure between two gates is unintentionally etched, causing the surface to become lower than the surrounding area. This local step formation leads to filling defects (e.g., voids) when depositing an insulating layer for insulating one gate line from another.
FIG. 1 illustrates a plan view of a typical semiconductor device. A device isolation structure 12 is formed on a substrate 11 to define an active region 13. A plurality of gate lines G are formed over the substrate 11.
FIG. 2 illustrates a cross-sectional view taken along cut plane A-A′ of FIG. 1, showing the limitations in the typical semiconductor device. The gate lines G are formed over the device isolation structure 12. However, prior to forming the gate lines G, the device isolation structure 12 has different heights in different regions. For instance, numerous wet etchings including cleaning are performed prior to forming the gate lines G. During the wet etchings, interfacial regions between the active region 13 and the device isolation structure 12 are likely to be damaged.
The damage is greater in a narrow region B where the space between the neighboring active regions 13 is small than in a wide region C where the space between the neighboring active regions 13 is large. The reason for this behavior is that the loss of the device isolation structure 12 is great in the interfacial regions with the active region 13 in the narrow region B. In addition to this loss, as reference letter ‘E’ in FIG. 3 illustrates, the device isolation structure 12 defined between the neighboring active regions 13 is lost in a horizontal direction as much as a minimum distance between the active regions 13. In other words, the etching is done more heavily in the narrow region B than in the wide region C, thereby resulting in the greater loss of the device isolation structure 12 in the narrow region B.
Accordingly, even though the narrow region B and the wide region C are applied with the same number of wet etching, the loss of the device isolation structure 12 is much severe in the narrow region B than in the wide region C. As a result, the device isolation structure 12 has different height in different regions.
FIGS. 4A and 4B illustrate cross-sectional views showing a typical method for fabricating a semiconductor device. Referring to FIG. 4A, a plurality of gate lines G are formed over the device isolation structure 12 of which part of the surface is removed to a depth D, and a gate spacer 14 is formed on both sidewalls of each of the gate lines G. An interlayer dielectric 15 is deposited on the resultant structure including the gate lines G.
Referring to FIG. 4B, a chemical mechanical polishing (CMP) or an etch back process is performed for planarizing the top surface of the interlayer dielectric 15 until the top surfaces of the gate lines G are exposed. As a result, neighboring gate lines G are insulated from each other.
As described above, according to the typical method, the surface loss of the device isolation structure 12 is not generated in a wide region C, whereas the device isolation structure 12 is removed to a depth D in a narrow region B where the space between the active regions is relatively small. As a result, a step formation is undesirably formed between the narrow region B and the wide region C. Thus, the gates formed around the narrow region B has a higher aspect ratio than the wide region C so that the interlayer dielectric 15 is not fully filled into the narrow region. This pattern may lead to a void V between the gate lines G, and a device failure may occur in subsequent manufacturing processes.